1. Field of the Invention
The present invention relates to integrated circuits and, more particularly, to an integrated circuit and a method of forming the integrated circuit with improved logic transistor performance and SRAM transistor yield.
2. Description of the Related Art
A system on a chip (SoC) is an integrated circuit that includes all of the elements required by an electronic device. A SoC often includes NMOS logic transistors, NMOS static random access memory (SRAM) transistors, and a number of resistors. The logic and SRAM transistors have gates which are commonly implemented with polycrystalline silicon (polysilicon). The resistors are also commonly implemented with polysilicon.
The fabrication of integrated circuits includes the formation and subsequent removal of a number of patterned photoresist layers. The formation and removal of patterned photoresist layers is a relatively expensive process. As a result, it is desirable to use the minimum possible number of patterned photoresist layers to reduce the fabrication costs.
One approach to minimize the number of patterned photoresist layers that must be used during the fabrication of a SoC is to form a patterned photoresist layer, and then simultaneously implant an n-type dopant into the regions of a polysilicon layer that will function as the logic gates and the SRAM gates.
A separate patterned photoresist layer is used to implant an n-type dopant into the regions of the polysilicon layer that will function as the resistors, which have a different dopant concentration than the logic and SRAM gates, to meet sheet resistance and temperature coefficient of resistance (TCR) targets.
One drawback to simultaneously implanting an n-type dopant into the regions of a polysilicon layer that will function as the logic gates and the SRAM gates is that the optimal dopant concentration for the logic gates is substantially different from the optimal dopant concentration for the SRAM gates.
The performance of the NMOS logic transistors improves with higher dopant concentrations, while higher dopant concentrations reduce the yield of the NMOS SRAM transistors. (Higher dopant concentrations in the logic gates reduce the effective gate dielectric thickness at inversion, which improves performance. However, higher dopant concentrations also lead to SRAM transistor cross diffusion where the n-type dopants from the n-type gate regions diffuse over into p-type gate regions. The diffusing n-type dopants reduce the effective p-type dopant concentrations in the p-type gate regions which, in turn, causes threshold voltage shifts and thereby a lower SRAM yield.) Conversely, the performance of the NMOS logic transistors degrades with lower dopant concentrations, while lower dopant concentrations improve the yield of the NMOS SRAM transistors.
Thus, the dose of the n-type dopant used to simultaneously implant the NMOS logic and SRAM transistor gates is commonly selected to be a comprise value that is less than the optimal dopant concentration for the logic gates and more than the optimal dopant concentration for the SRAM gates.